This invention relates generally to a method of operating semiconductor memory cells, and in particular to a method of operating dynamic semiconductor memory cells with capacitive means for the storage of binary data.
The economies relevent to semiconductor random access memories make it desirable to minimize the semiconductor surface area required per stored bit, and thus to use minimum size memory cells, such as the one transistor memory cell. However, memories utilizing such minimum size memory cells often do not include features such as content addressing capability and nondestructive recall capability.
In general most semiconductor memory cells with content addressing capability can also be operated as random access memory cells with nondestructive recall. Also the combination of two random access memory cells with nondestructive recall capability can often be used as a content addressable memory cell. Therefore, although content addressability and nondestructive recall are usually considered unrelated properties of a memory cell, they are in fact closely related.
In the prior art, several types of memory cells with nondestructive recall have been developed. For example, the memory cell described in the copending patent application filed by the present inventor entitled "Semiconductor Device for the Storage of Binary Data", Ser. No. 613,189, filed on Sept. 15, 1975, now U.S. Pat. No. 3,997,799, provides for nondestructive recall. Also memory cells with a minimum of three transistors have been developed which provide nondestructive recall. In the past dynamic semiconductor memory cells with nondestructive recall have not found widespread use because the disadvantages of prior art designs, such as the relatively large number of components required per memory cell, the relatively large power consumption of such memory cells, and the large area required per memory cell, outweigh the advantages.
Several different types of content addressable memory cells have also been developed in the prior art. For example, a five transistor memory cell for use in associative memories has been described by J. L. Mundy, J. F. Burgess, R. E. Joynson, and C. A. Neugebauer in the Digest of Technical Papers Presented at the 1972 IEEE International Solid-State Circuits Conference, pp. 58. A three transistor memory cell which is claimed functions as an associative memory cell despite the admitted limitation to searching only for 1's has been described by R. M. Lea in the IEEE Journal of Solid State Circuits, June 1975, pp. 179. Finally several nine transistor associative memory cells have been described by J. T. Koo in the IEEE Journal of Solid State Circuits, Vol Sc-5, October 1970, pp. 208. All of the above mentioned associative memory cells require considerable semiconductor surface area relative to the minimum size memory cells, and have not found widespread use.